1. Field of the Invention
The present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of electrically conductive lines provided in an integrated circuit.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors formed on and in a substrate. These elements are connected internally by means of electrically conductive lines to form complex circuits such as memory devices, logic devices and microprocessors. To accommodate all the electrically conductive lines required to connect the circuit elements in modern integrated circuits, the electrically conductive lines are arranged in a plurality of levels stacked on top of each other. To connect electrically conductive lines provided in different levels, contact vias are formed in dielectric layers separating the levels from each other. These vias are then filled with an electrically conductive material.
A method of forming an electrically conductive line according to the state of the art will now be described with reference to FIGS. 1a-1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the method of forming an electrically conductive line according to the state of the art.
A semiconductor substrate 101 is provided. The semiconductor substrate 101 may comprise a plurality of circuit elements and, optionally, electrically conductive lines in lower interconnect levels. The semiconductor substrate 101 further comprises a first dielectric layer 102 formed thereon. A trench 107 is formed in the layer 102. In the trench 107, a trench fill 111 comprising an electrically conductive material, for example a metal such as copper, is provided. The trench fill 111 forms an electrically conductive line. A diffusion barrier layer 110 separates the trench fill 111 from the first dielectric layer 102. Thus, a diffusion of the material of the trench fill 111 into the first dielectric layer 102 can be prevented and an adhesion between the trench fill 111 and the dielectric material of the first dielectric layer 102 can be improved. The semiconductor substrate 101 can be formed by means of methods known to persons skilled in the art comprising advanced techniques of deposition, oxidation, ion implantation, etching and photolithography.
An etch stop layer 103 is formed over the semiconductor substrate 101. In addition to the surface of the first dielectric layer 102, the etch stop layer 103 covers an exposed top surface of the trench fill 111. A second dielectric layer 104 is formed on the etch stop layer 103. The second dielectric layer 104 may comprise the same material as the first dielectric layer 102. The etch stop layer 103 and the second dielectric layer 104 may be formed by means of methods known to persons skilled in the art, such as chemical vapor deposition, plasma enhanced chemical vapor deposition and spin coating.
A trench 109 and a contact via 108 are formed in the second dielectric layer 104. This can be done by photolithographically forming a mask (not shown) which exposes a portion of the surface of the second dielectric layer 104 at the location where the contact via 108 is to be formed. Then, an etching process is performed. To this end, the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the material of the second dielectric layer 104, leaving the etch stop layer 103 essentially intact. Thus, the etching process stops as soon as the etch front reaches the etch stop layer 103.
The etching process may be anisotropic. In anisotropic etching, a rate at which material is removed from the etched surface depends on the orientation of the surface. The etch rate of substantially horizontal portions of the etched surface being substantially parallel to the surface of the semiconductor substrate 101 is significantly greater than the etch rate of inclined portions of the etched surface. Thus, substantially no material below the mask is removed and the via 108 obtains substantially vertical sidewalls. Thereafter, the mask is removed, which can be done by means of a resist strip process known to persons skilled in the art, and the trench 109 is formed. Similar to the formation of the contact via 108, the trench 109 can be formed by photolithographically forming a mask on the semiconductor structure 100 and performing an anisotropic etching process.
Subsequently, a portion of the etch stop layer 103 exposed at the bottom of the contact via 108 is removed. The exposed portion of the etch stop layer 103 can be removed by means of an etching process adapted to selectively remove the material of the etch stop layer 103, leaving the materials of the second dielectric layer 103 and the trench fill 111 substantially intact.
A diffusion barrier layer 105 is deposited on the semiconductor structure 100. In particular, the diffusion barrier layer 105 covers the sidewalls and the bottom of the trench 109 and the contact via 108. This can be done by means of known methods such as chemical vapor deposition, plasma enhanced chemical vapor deposition and/or sputter deposition. Then, a layer 106 of an electrically conductive material is formed on the diffusion barrier layer 105. To this end, methods of electroplating known to persons skilled in the art may be employed.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a further stage of the method of forming an electrically conductive line according to the state of the art.
The surface of the semiconductor structure 100 is planarized, for example, by means of a known chemical mechanical polishing process. In the planarization, portions of the diffusion barrier layer 105 and the layer 106 outside the trench 109 and the contact via 108 are removed and a planar surface of the semiconductor structure 100 is obtained. Residues of the layer 106 in the trench 109 form an electrically conductive line. Residues of the layer 106 in the contact via 108 provide an electrical contact between the electrically conductive lines in the trench 109 and the trench 107.
A problem of the semiconductor structure 100 is that an adhesion between the layer 106 of electrically conductive material in the contact via 108, the diffusion barrier layer 105 and/or the trench fill 111 may be relatively low. When the chemical mechanical polishing process is performed to remove the portions of the diffusion barrier 105 and the layer 106 outside the trench 109 and the contact via 108, mechanical stress may be created in the semiconductor structure 100. Moreover, mechanical stress may be created in the semiconductor structure 100 in later steps of the manufacturing of the semiconductor structure 100 or the operation of the semiconductor structure 100. In the operation of the semiconductor structure 100, heat may be created due to the electrical resistivity of the materials in the trench 107, the contact via 108 and the trench 109. Since the thermal expansion coefficient of individual materials in the semiconductor structure 100 may be different, the creation of heat may lead to mechanical stress in the semiconductor structure 100. Such mechanical stress may lead to a separation of the layer 106 of electrically conductive material in the contact via 108, the diffusion barrier layer 105 and/or the trench fill 111 which may adversely affect the functionality of the semiconductor structure 100 and may even lead to a failure thereof.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.